IL2201 Digital Integrated Circuit Design vlsi interconnect Design -transmission Lines

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IL2201 Digital Integrated Circuit Design

Interconnect Design -Transmission Lines

Home reading: B2-3.3, 3.4, B1-4.4.5B1-ch.9 9.4


.Lecture 1. Course Overview & Introduction (Ch.1 & Ch.4).Lecture 2: Wires as Interconnects in VLSI ( B1 Ch4 & 9).Lecture 3. Interconnect Design – transmission lines (Ch.3).Lecture 4. Noise in Digital Systems (Ch.6, B1 Ch.9).Lecture 5. Noise (continue) (Ch.6).Lecture 6. Signaling Conventions (Ch.7).Lecture 7. Signaling Techniques (Ch.8 & 11).Lecture 8. Power Distribution Design (Ch.5).Lecture 9: Timing Conventions (Ch.9 & B1 Ch.10).Lecture 10: Clock Distribution Design (Ch.9 & B1 Ch.10).Lecture 11: Synchronization (Ch.10 B1 Ch.10 ).Lecture 12: Synchronizer Design (Ch.10).Lecture 13: Signaling and Timing Circuits (Ch.11 & 12


Interconnect models

RC vs LC behaviour

RC vs. LC behaviour

Wire Models

.In each design task, we create a model of a wire that captures the properties we need Lumped C

  1. – ideal

  2. – lumped L, R, or C

  3. RC transmission line

  4. LC transmission line

  5. general LRCG transmission line

.Model to use depends on the Lumped L and C frequency of the signal:

cutoff frequency of the line !

. fsignal < f0 => RC line (R dominates over L) fsignal > f0 => LC or LRC line (L dominates over R)

Infinitesimal LRCG Wire Model

.Model an infinitesimal length of wire, dx, with the components:

  1. L = series inductance per unit length

  2. R = series resistance per unit length

  3. C = parallel capacitance per unit length

  4. G = parallel conductance per unit length between the signal and ground wires

. Theoretical model — not usable in practical simulation tasks

Lumped LRCG Model for Simulation

.Divide the transmission line into sections of the length Δx and model each section by its lumped L, R, C and G

.If Δt is the timestep used by the simulator, and tr is the shortest expected rise time in the line (i.e. 1/(2tr ) is the highest frequency!), then, as a rule of thumb, the length Δx should be selected in such a way that

Δt <<2πΔx LC <<2



where 1/(2πΔx

LC )is the resonant frequency of a

wire section

Transmission Line Equations


= RI + L

  1. Voltage drop across R and L : x t I V

  2. Current into C and G :∂x = GV + C t

Differentiating 1 with respect to x and substituting 2 into the result gives: ∂2V V 2V

=RGV +(RC +LG) +LC

x2 t t2

Lossless LC lines

. .

If R and G are negligible – line is lossless (no attenuation) – governed by the wave equation Waves propagate down the line in both directions without distortion

2 2 2 2 t VLC x V ∂∂=∂∂2 1 )( =LCv

where, 1 2 2 2 t V v ∂∂=2 1 0 ⎟⎠⎞⎜⎝⎛=C LZ


Line is described by its impedance Z0 and velocity v

Lossless LC line

. The wave equation

2V 1 ∂2V 1 x2 = v2 t2 ⎜⎜v =(LC)2 ⎟⎟

has solutions of the form:

Vf (x,t) =V 0,t x (Forward wave)
⎝ v ⎠

V (x,t) = V x ,t xmax − x (Reverse wave


r max


. Waveform on the line is superposition of forward and reverse traveling waves !!

Driving a Transmission Line

.Place waves on the line by driving one end with a voltage source V(t) which has an output impedance R0. Assume that the line is infinite for now.

Driving a Line —Equivalent Circuit

.Response of the line to the voltage source V(t) depends on the previous state of the line, i.e., the voltage VC to which the capacitance C of the line has been previously charged

.When VC = 0, the wave propagating along the line is said to be the first incident wave

Load Termination

.Suppose we drive a unit step U(t) on the line which is terminated in an impedance of ZT

. What happens in the far end?

Incident wave, i.e., forward traveling wave injected into the line

Termination —Equivalent Circuit

Vi = amplitude of the incident wave at the end of the line ( = Vi (xmax,t) )

.In the model, the voltage is 2Vi or twice the amplitude of the incident wave at the end of the line in order to get the voltage Vi on the line when ZT = Z0 (divide-by-two voltage divider)

Some Common Terminations

Open-circuit termination

ZT − Z0

k =


ZT + Z0

ZT =∞, kr = 1

Reflection doubles the voltage !

ZT = Z0, kr = 0

No reflection !

ZT =0, kr =−1

Reflection cancels the voltage !


.Incident wave determines Vi , Ii .Use the equivalent circuit to solve for VT , IT .Use superposition to calculate Vr , Ir

kr =

KTH/Li-Rong Zheng

Matched Termination

Series Source Termination

Source-Terminated Line

.Half of VT is first injected into the line (divide-by-two voltage divider !). A full reflection at the receiver side doubles VB to the full amplitude. VA at the trans-mitter side follows one line delay later.

. Source termination prevents multiple reflections and absorbs noise at the source.

.Many systems provide matched terminations for both ends of the line.

Example of Reflections

k = T 0


ZT + Z0

Example of Reflections


Vline =⋅1V


400 +1000 = 0.714 V

Without a matched termination at least at one end of the line a significant delay or intersymbol interference is introduced !!

Tunable Segmented Matched Line Driver

Equivalent Output resistance Req= Zo

Parallel Termination─ Transistors as Resistors

Vdd R



2 Mr 1.9 NMOS only



PMOS only

Out 1.6


1.4 Vdd Vdd 1.3

1.2 Mr 1.1 PMOS with-1V bias















Vbb 0 0.51 1.5 2 2.5 VR (Volt


Out Out

Output Driver with Varying Terminations





4 V 3

2 2

1 1

0 0

1 0123456781 time (sec)


Lossy Transmission lines

Lossy Transmission Lines

.LC lines with resistance R and conductance G

  1. – propagation governed mostly by the wave equation (LC)

  2. – … and some by the diffusion equation (RC)

.R and G dissipation

  1. – reduces the amplitude of the signal

  2. – disperses the signal » fast rise to AC (wave) attenuation » slow tail to DC attenuation

. Resistance and conductance depend on frequency

– we return to this a bit later

Example: Step Response of a 1 m/0.2 mm Stripline

Wave Attenuation

.The magnitude of the traveling wave, Vi (x), at .Using Taylor series we get: any point x of the line is related to the initial magnitude Vi (0) by A j


LC 1− j RC + GL

Vi (x) =Vi (0)exp(−Ax) or Vi (x) =exp(−Ax)1
i (0)

= jω LC + R + GZ0, Z0 =L 2


2 ⎝ C

where A =[(G +jωC)(R +jωL)]12

is the propagation constant of the linePhase shift Amplitude loss

.Assuming that G and R are relatively small .Hence, the amplitude at any point x, with at high frequencies we can rewrite A as respect to the initial amplitude, can be written as


A ≈( jωRC +jωGL −ω2 LC)2 |V (x)| =exp[−(αR D )x



1|Vi (0)|⎛RC +GL 2 = jω LC

⎜1− j ωLC where the attenuation factors αR and αD are given by

αR = R Loss in the resistance R 2Z per unit length


αD = GZ0 Dielectric loss in the conductance G 2 per unit length

DC Attenuation

. DC conductance of the dielectric (insulator) is zero in most real transmission lines. Hence, only the resistance of the conductor causes a significant DC attenuation

.Consider a line of the length d with the matched termination Z0. The output voltage across Z0, denoted VDC(d), is related to the initial DC voltage VT by

VDC (d ) = Z0 = 1

VT Rd + Z0Rd +1

αR = R (Attenuation factor)2Z0

Attenuated Waveform

Attenuation Closes the Eye Diagram

.Critical parameter is what fraction of swing, A, is obtained in one bit time

.Eye opening is reduced to B = 2A-1

.No eye opening at 50 % attenuation (A =

0.5 => B = 0)

. Significant degradation of margins at lower levels of attenuation

Skin Effect

.Current density J in a conductor drops off exponentially with depth d

.Skin depth δis the depth where the current has decreased to 1/e (37 %) of its maximum value on the conductor surface

.Skin depth δdepends on the frequency f of the traveling signal, the conductivity σ[1/resistivity (ρ)] of the wire material, and the permeability μof the surrounding medium

.Because δ~ f , high-frequency currents flow primarily on the surface of a conductor !!

.Skin effect is modeled by assuming that all current flows in the δ-thick outer layer of the conductor. The cross-sectional area A that is carrying current is then

given by: Rectangular wire:



A ≈2πrδ=2πrfμσ)2 (Round wire) h



A ≈2wδ=2wfμσ)2 (Rectangular wire) w

KTH/Li-Rong Zheng

Skin-Effect Resistance

.Effect occurs when the signal frequency exceeds the skin depth frequency fs , where the skin depth is equal to the radius r of a round conductor or half of the height h of a rectangular conductor:

ρ ρ

fs =πμ r2 (Round wire) fs =πμ(h /2)2 (Rectangular wire)

.Skin-effect resistance R(f) per unit length, where f fs , is given as

1 1

R( f ) =1 fμρ⎞ 2 = RDC f 2, RDC =ρ 2 (Round wire)

2r π2 fs π r


11 ⎛ f ⎞ 2 ρ

R( f ) =(πfμρ)2 = R ⎟, R =(Rectangular wire)2w DC fs DC wh

.Hence, above the frequency fs , the resistance increases as the square-root of frequency !!

Resistance and Attenuation of a Stripline


.w = 125 μm, h = 20 μm, skin-effect attenuation factor: αS ( f ) =RDC f 2 2Z0 ⎝ fs

50 Ω/m RDC = 7 Ω/m

ADC = 0.90 m -1

0.40 m -1

Dielectric Absorption

.High-frequency signals jiggle molecules in the insulator. Hence, the insulator absorbs signal energy !

.This effect is approximately linear with the signal frequency and is modeled as a conductance G

.Dielectric loss is often specified in terms of a loss tangent, denoted tan(δ)

KTH/Li-Rong Zheng



1 c

v ==

LC ε


v = speed of the wavec = speed of light in vacuumεr = relative permittivity of

the insulator material

Skin-Effect Resistance and Dielectric Absorption

. Example: 1 m/0.2 mm stripline with GETEK dielectric

Bd2 Constant

.Suppose you can tolerate a certain attenuation A

eye opening is 2A-1 .At a certain bandwidth B1 attenuation A is achieved with a distance of 1 m .As the bandwidth is increased to B, resistance, and hence attenuation, is increased with B ½ .In order to maintain the initial attenu­ation level, the distance d must be decreased so that the product Bd 2 equals the initial bandwidth B1 .For example, if B = 4B1, the distance must

be halved. Or if the distance is doubled, the bandwidth is limited to B = B1/4

A(B1,1m) = A1

1 B 2

A(B, d ) =A1d⎟ ⎝ B1 ⎠requirement: A(B, d ) =A1

Bd 2 = B1

Multi-Drop Buses

. At any given point in time, one module is authorized to transmit data and the other modules listen

. Any module can communicate with any other module

. Bus speed is limited by geometry of the bus:

– stub length and stub spacing



Z = Lv =
KTH/Li-Rong Zheng C



Example Bus

. Zb = Zs = 50 Ω

  1. C = 150 pF/m, L = 375 nH/m, Z = (L/C)½ . Zx = 15 pF, Cs = 150·0.1 pF = 15 pF (transceiver & stub capacitances)

  2. adds 30 pF of load every 3 cm, or 1 nF/m .Hence, the bus-stub-transceiver combination has a capacitance of 1.15 nF/m – m/s (1/3 of the normal speed) .High-impedance, high-swing drivers need

several round trips to ring up the low-impedance bus to a detectable voltage level

causes a considerable delay, together with the low RT

    1. Example : 30 cm bus, 6 ns/traversal, 5 traversals needed => 30 ns delay (33 MHz) .A sharp signal edge traveling down the bus reflects partially back from each stub

    2. rise/fall time of a signal, tr , must be significantly longer than the round-trip delay td of a stub. A rule of thumb: tr > 5td

  1. Example: td = 1.4 ns => rise/fall times must be 7 ns or longer .Leaving a module “unplugged” (a free slot) causes an impedance mismatch and hence

KTH/Li-Rong Zheng

significant reflections (a 50 Ω-section surrounded by 18 Ω-lines )

1/22/2009 40

Multi-Drop Buses vs Point-to-Point Architectures

. Point-to-point links can signal 5-10 times faster than buses

. Point-to-point architectures are rapidly replacing bus architectures in high-speed systems

Bus architecture

Point-to-point architecture

Balanced Lines, Modeling, Design, and Wire Costs

Balanced (Symmetric) Transmission Lines

.A transmission line has a signal path and a return path (“ground”)

.All real transmission lines have a nonzero inductance also in the return path, so that the total inductance per unit length L is the sum of the inductances per unit length in the signal and return paths: L = Ls + Lr

.For coaxial cables and striplines between large return planes Lr is much less than Ls and can often be ignored

.In a balanced line, the return

0.5 V

inductance Lr equals the signal 1 V

1 V inductance L: L= L

s sr

voltage drops across Ls and Lr are
equal but opposite in direction

-0.5 V

Pair of Coupled Transmission Lines

. Consider a pair of signal wires which are balanced or symmetric with respect to each other, so that their inductances are equal


.M (mutual inductance) and Cd represent coupling between the two lines

.L and Cc represent coupling to other conductors

For example, a pair of strip guides between ground planes

Common-and Differential-Mode Signals

A wave has two possible propagation modes: .Common-mode signal V1

  1. both lines are tied together and driven with the same

  2. equal currents flow in the two lines in the same

direction V2 .Differential-mode signal

  1. the signal is applied differentially across the two lines

  2. equal currents flow in the two lines in opposite directions V1

.The voltages V1 and V2 applied to the two lines can V2 be viewed as the combination of a common-mode voltage VC and a differential-mode voltage VD

VC = V1 +V2 VD = V1 −V2 Example: 1 V step (V1=1 V, V2=0): 22 VC = 0.5 V, VD = 0.5 V

Common-and Differential-Mode Impedance

. Common mode

  1. – parallel currents increase the effective inductance by M

  2. parallel voltage transitions cancel the effect of Cd

1 ZC = VC =⎜⎜ L +M ⎟⎟ 2 I1 ⎝ C − Cd

. Differential mode . Common-and differential-mode signals

opposite currents reduce the effective see different impedances! inductance by M .Increasing the coupling capacitance Cd, – opposite voltage transitions double the for example by reducing the distance effect of Cd between the two wires, gives a better 1 differential line, as ZD is reduced and ZC Z = VD =⎜⎜L − M ⎟⎟2 is increased


I1 ⎝ C + Cd

Example of Common-and Differential-Mode Impedances

Termination of a Balanced Line

.In a balanced termination, the common-and differential-mode impedances are matched simultaneously

  1. common-mode signals terminated with the impedance ZC

  2. differential-mode signals terminated with the impedance ZC || RP which equals ZD, if











.Unbalanced termination causes mode coupling, i.e., energy is exchanged between the common-mode wave and the differential-mode wave at each reflection

– leads to intersymbol interference

Modeling of Real Signal Paths

. Given a real system

– chips, packages, boards, connectors, backplanes, cables

.Need to develop a model of the signaling medium

– for hand calculation of key properties

– for SPICE simulations . Model must

  1. – capture all relevant wire properties » transmission line properties » major discontinuities » terminations

  2. ignore properties that are not relevant » for example short discontinuities

Example Model

Deriving and Using a Model

. Create first detailed physical models of the line components (striplines, cables, connectors, packages, etc.)

use data books provided by the component vendors

. Create an electrical model by computing the electrical parameters from the physical model

– hand calculation

– a CAD tool . Simulate the electrical model using for example SPICE . Validate the electronic model in the laboratory after the components of the

line have been fabricated

use for example the time-domain reflectometer (TDR )

Wire Costs — Area

.Modern digital chips are often wire-limited, i.e., the area (and hence the cost) of a chip is determined by the required wiring rather than the number of transistors.

.The area of a chip is expressed as the number of wire grids

number of grids = horizontal tracks * vertical tracks .A grid has a technology-dependent cost –0.35 μm technology in 1996: unit cost = 3.1 ·10 -7 $/grid, => 15*15 mm2 chip with 1.6 ·108 grids: cost = $50

. Off-chip wiring on a circuit board is 100-1000 times more expensive per grid than the wiring on a chip

– a major reason why integration pays off !!

Wire Costs — Pins

.If a chip is pin-limited, the cost is dominated by the area required by the bonding pads. In other words, the number of I/O terminals is large compared to the size of logic and its wiring

.Selected bonding method affects the cost In 1996:

peripheral-bonded chip (pads surround the logic core): 11 cents/pin

area-bonded chip (pads utilize the entire area of the chip): 1.4 cents/pin .Selected package affects the cost

  1. plastic packages are inexpensive (about 1 cent/pin) but have poor electrical properties

  2. ceramic packages with power planes, multiple signal layers, and heat slugs can be very expensive (about 10 cents/pin)


. Transmission Line Model . Load and source termination . Lossy transmission lines . Multi-drop bus . Balanced lines

Next Lecture: Noise in Digital Systems

Home reading: Ch.6

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