Scaling to the end of silicon with edge architectures




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Scaling to the end of silicon with EDGE architectures


Burger, D.; Keckler, S.W.; McKinley, K.S.; Dahlin, M.; John, L.K.; Lin, C.; Moore, C.R.; Burrill, J.; McDonald, R.G.; Yoder, W.;
Computer
Volume 37,  Issue 7,  July 2004 Page(s):44 – 55
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Sankaralingam, K.; Nagarajan, R.; Haiming Liu; Changkyu Kim; Jaehyuk Huh; Burger, D.; Keckler, S.W.; Moore, C.R.;
Computer Architecture, 2003. Proceedings. 30th Annual International Symposium on
9-11 June 2003 Page(s):422 – 433
Routed inter-ALU networks for ILP scalability and performance
Karthikeyan Sankaralingam; Vincent Ajay Singh; Keckler, S.W.; Burger, D.;
Computer Design, 2003. Proceedings. 21st International Conference on
13-15 Oct. 2003 Page(s):170 – 177
Static placement, dynamic issue (SPDI) scheduling for EDGE architectures
Ramadass Nagarajan; Kushwaha, S.K.; Burger, D.; McKinley, K.S.; Lin, C.; Keckler, S.W.;
Parallel Architecture and Compilation Techniques, 2004. PACT 2004. Proceedings. 13th International Conference on
29 Sept.-3 Oct. 2004 Page(s):74 – 84

RAW


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Baring it all to software: Raw machines
Waingold, E.; Taylor, M.; Srikrishna, D.; Sarkar, V.; Lee, W.; Lee, V.; Kim, J.; Frank, M.; Finch, P.; Barua, R.; Babb, J.; Amarasinghe, S.; Agarwal, A.;
Computer
Volume 30,  Issue 9,  Sept. 1997 Page(s):86 – 93
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
Taylor, M.B.; Kim, J.; Miller, J.; Wentzlaff, D.; Ghodrat, F.; Greenwald, B.; Hoffman, H.; Johnson, P.; Jae-Wook Lee; Lee, W.; Ma, A.; Saraf, A.; Seneski, M.; Shnidman, N.; Strumpen, V.; Frank, M.; Amarasinghe, S.; Agarwal, A.;
Micro, IEEE
Volume 22,  Issue 2,  March-April 2002 Page(s):25 – 35
"Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures", by Michael Bedford Taylor, Walter Lee, Saman Amarasinghe and Anant Agarwal, In Proceedings of the International Symposium on High Performance Computer Architecture, February 2003
"Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine", by Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, and Saman Amarasinghe.

Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, October 4-7, 1998.


compiler(very brief) + evaluating(more detailed) Section 4(pages 6-9) of "The Raw Compiler Project", by Anant Agarwal, Saman Amarasinghe, Rajeev Barua, Matthew Frank, Walter Lee, Vivek Sarkar, Devabhaktuni Srikrishna, and Michael Taylor.

Proceedings of the Second SUIF Compiler Workshop, Stanford, CA, August 21-23, 1997.

"Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams", by Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal.

Proceedings of International Symposium on Computer Architecture, June 2004.







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