Introduction to the S12 A/D converter system me 4370/5370 Introduction




Yüklə 55.19 Kb.
tarix20.04.2016
ölçüsü55.19 Kb.
Introduction to the S12 A/D converter system

ME 4370/5370


Introduction:

The MC9S12 contains two eight-channel, 10-bit A/D converter with +/- 1 LSB accuracy. Port AD bits PADx0-PADx7 are the analog input pins which are sampled and converted to 10-bit digital values. The results of the A/D conversion are placed in the data registers ADRxDnH, ADRxDnL. There are several A/D control registers, named ATDxCTL1 – ATDxCTL5, ATDxStat, which control the operation of the A/D. These registers must be initialized to perform the A/D process. These will be described in the following sections. In addition, a single reference voltage state must be physically set over the pins VRH and VRL (see the breakout board for these pins). VRH must not exceed 6V, and VRL must not go below 0V. The range VRH - VRL must be greater than or equal to 0 V. Using this reference range, all analog inputs are converted to a value using a linear conversion over this range. For example, if VRH = 5V and VRL = 0V, then an analog input of 2.5 V would be converted to a digital number of ½*28 or ½*256 or 127 (1 V input would be converted to 1/5*28 or 1/5*256). Note that the resolution is given as:



resolution = (VRH - VRL)/2n.
How the S12 ATD system works:

“The Analog-to-Digital (A/D) Machine performs analog to digital conversions. The resolution of the A/D converter is program selectable at either 8 or 10 bits. This machine uses a successive approximation A/D architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the converter locates the approximating potential that is nearest to the sampled potential.”



Procedure to Use A/D Converter:


Step 1: Power up the ATD system using ATDxCTL2 (ATD ConTroL register 2, $0002 offset).

This register and the basic control bits are shown below. Of primary importance is the ADPU bit (A/D power up bit), which must be set to one to power up the A/D, and the interrupt enable bits if desired. For example, writing $80 to ATDxCTL2 will power up the A/D. After power-up, a 100 microsec. delay is required before using the A/D.



ATDxCTL2 -- $0002 – ATD Control Register 2




with

ADPU: ATD Power up

0 = Disables A/D for reduced power consumption (default)

1 = Allows the A/D to function normally

A short time delay of 100 micro seconds should be executed after powering up the A/D to allow all analog circuits to be stabilized.


ASCIE: ATD Sequence Complete Interrupt Enable
ASCIF: ATD Sequence Complete Interrupt Flag
Step 2:

After power-up (Step 1), a 100 microsec. delay is required before using the A/D.


Step 3:

Set the conversion sequence mode using ATDxCTL3 (ATD ConTroL register 3, $0003 offset). This register controls the number of samples per conversion that are to be performed.



ATDxCTL3 -- $0003 – ATD Control Register 3



S8C/S4C/S2C/S1C: Conversion Sequence Length

These represent a binary value which is the length of the conversion sequence (as in Table 98, advanced S12 Information Manual)



Result Register Assignments:

These bits also determine the result register assignments. The first result is placed in the first register, and so on. This is demonstrated in Table 99:



Step 4: Set sampling and conversion time. The sampling and conversion time can be controlled, with ATDxCTL4 (offset $0004, address $0064). It is advised to use the default values. The general rule of thumb is that high-impedance sources require a longer sample time. Therefore, no action needs to be taken in step 3 for basic implementation



ATDxCTL4 -- $0064 – ATD Control Register 4

Bit 7 6 5 4 3 2 1 bit 0




SRES8

SMP1

SMP0

PRS4

PRS3

PRS2

PRS1

PRS0

Reset 0 0 0 0 0 1 0 1


with

SRES8: A/D resolution select 0 = 10 bit resolution, 8 = 10 bit resolution
SMP1, SMP0: Sample Time Select Bits


Prescaler bits PRS4-PRS0

Total Divsor

Max P-Clock (MHz)

Max ATD Clk (MHz)

Min P-Clock (MHz)

Min ATD Clk (MHz)

00000

2

4

2

1

.5

00001

4 (default

8

2

2

.5

00010

6

8

1.33

3

.5

00011

8

8

1

4

.5

00100

10

8

.8

5

.5

00101

12

8

.667

6

.5

00110

14

8

.571

7

.5

00111

16

8

.5

8

.5

01xxx

do not use













11xxx

do not use
















SMP1

SMP0

Final sample time, ATD Clock periods

Total conversion time, ATD clk periods

Nyquist Frequency for 2 MHz ATD clk

0

0

2

18

55.5 kHz

0

1

4

20

50 kHz

1

0

8

24

41.7 kHz

1

1

16

32

31.25 kHz

Step 5: Set ATDCTL5. The ATDxCTL5 register ($0065, $0005 offset) controls the sampling modes and starts the conversion process. This is done through the following bits:

DJM – Data is justified left or right

DSGN – Data is signed or unsigned

SCAN – set for either a single scan sequence (0) or a continuous scan sequence (1)

MULT – set to allow conversion of a single channel (0) or multiple channels (1)

CC-CA – Selects the channel for conversion (when MULT=0)
Note: If conversion is to be completed on 1 channel, then 4 or 8 conversions on that one channel are performed and stored. If conversion is to be completed on multiple channels, then 4 or 8 channels are read and stored. The following charts provide more information on ATDCTL5 selection.

ATDCTL5 -- $0005 – ATD Control Register 5

Bit 7 6 5 4 3 2 1 bit 0




DJM

DSGN

SCAN

MULT

0

CC

CB

CA

Reset 0 0 0 0 0 0 0 0


with

DJM: Data Justified method

0 = Data is left justified

1 = Data is right justified
For 10-bit resolution, left justified mode places the result into result register bits 6 through 15 (15 is MSB). In right justified mode, the results is placed into bits 0 through 9 (9 is MSB). For 8 bit resolution, left justified placed the result in the high byte, right justified into the low byte.
DSGN: Sign of ATD

0 = Convert as unsigned values

1 = Convert as signed values
SCAN: Enable continuous channel scan

0 = Single conversion sequence each time ADTCTL5 is written (default)

1 = Continuous conversion sequences
MULT: Enable multichannel conversion

0 = All conversions are done on a single input channel selected by CC-CA (default)

1 = Each of the conversions are done on multiple channels

When Mult is 0, the ATD samples only from the specified analog input channel for the entire conversion sequence (selected by CC-CA). When Mult is 1, the ATC samples across x channels (Number of channels determined by S8C-S1C), and CC-CA determines the starting input channel for conversion, with following channels sampled in the sequence determined by incrementing channel selection code.


CC-CA: Channel select for conversion, as given on Table 105

Step 6: A/D Operation. The A/D conversion is started by writing to the ATDCTL5 register. Each conversion requires some number of clock cycles (refer to HC-12 reference manual). After the conversions are done, a sequence complete flag (SCF) is set in the A/D status register (ATDSTAT, $0066, $0067), and the result registers are ready to be read. The A/D is now waiting for another write to the ATDCTL5 register to begin another sequence (if SCAN=0) or will repeat the process (if SCAN = 1).

ATDSTAT -- $0066, (and $0067) – ATD Status Registers

Bit 7 6 5 4 3 2 1 bit 0




SCF

0

ETORF

FIFOR

0

CC2

CC1

CC0

Reset 0 0 0 0 0 0 0 0


with SCF the sequence complete flag. This bit is set at the end of the conversion sequence.
Step 7: Fetch digital results. The digital results are available in the ATDDRxH to ATDDRxH registers. The conversion is complete when the SCF flag is set in the ATDSTAT register. This register can be checked through a polling process. The SCF flag is cleared when the ATDCTL5 register is written (when AFFC = 0 in ATDCTL2). In addition, Conversion complete flags (CCFx) are contained in the low byte of ATDSTAT that indicate the end of the conversion for each associated channel.




Summary: A/D Programming


1. Power up the A/D by setting the ADPU bit in ATDCTL2

2. Wait for 100 microsec. Before using the A/D

3. Select number of conversions by setting ATDCTL3

4. Select the resolution and sample time, ATDCTL4

5. Choose DJM, DSGN, SCAN, MULT and CC-CA bits in ATDCTL5

6. Write to ATDCTL5 to start the conversion

7. Wait for the conversion sequence to complete by polling the SCF bit in ATDSTAT

8. Read the result in the ATDDR0H-ATDDR7H register



Example Program


The following example program demonstrates simple use of the A/D functionality in the HC12.
#include /* common defines and macros */

#include /* derivative information */

#include

#include "lcd.h"

#pragma LINK_INFO DERIVATIVE "mc9s12dp256b"

void main( void )

{

unsigned int i; //loop counter



unsigned int result; //used for calculating voltage

char display[17] = "Voltage = x.x "; // initalize string

LCD_init(); // Enable the LCD display

ATD1CTL2 = 0x80; //normal A2D operation initialization

for(i = 0; i < 1000; i++); //delay for initialization

ATD1CTL3 = 0x08; // 1 conversion per scan

ATD1CTL5 = 0x20; //continuous scan on AD1 channel 0 (PAD8)

while(1)


{

while(!(ATD1STAT0 & 0x80)); //wait for scan conversion to complete

result = (float) ATD1DR0H / 0.051; %result in millivolts

sprint(display, ‘The result is %d’,result);

writeLine(display, 0); //write to screen

}

}








Verilənlər bazası müəlliflik hüququ ilə müdafiə olunur ©azrefs.org 2016
rəhbərliyinə müraciət

    Ana səhifə