IL2201 Digital Integrated Circuit Design
VLSI
Interconnect Design Transmission Lines
Home reading: B23.3, 3.4, B14.4.5B1ch.9 9.4
Navigation
.Lecture 1. Course Overview & Introduction (Ch.1 & Ch.4).Lecture 2: Wires as Interconnects in VLSI ( B1 Ch4 & 9).Lecture 3. Interconnect Design – transmission lines (Ch.3).Lecture 4. Noise in Digital Systems (Ch.6, B1 Ch.9).Lecture 5. Noise (continue) (Ch.6).Lecture 6. Signaling Conventions (Ch.7).Lecture 7. Signaling Techniques (Ch.8 & 11).Lecture 8. Power Distribution Design (Ch.5).Lecture 9: Timing Conventions (Ch.9 & B1 Ch.10).Lecture 10: Clock Distribution Design (Ch.9 & B1 Ch.10).Lecture 11: Synchronization (Ch.10 B1 Ch.10 ).Lecture 12: Synchronizer Design (Ch.10).Lecture 13: Signaling and Timing Circuits (Ch.11 & 12
)
Interconnect models
RC vs LC behaviour
RC vs. LC behaviour
Wire Models
.In each design task, we create a model of a wire that captures the properties we need _{Lumped }_{C}
_{ }

– ideal

– lumped L, R, or C

– RC transmission line

– LC transmission line

– general LRCG transmission line
.Model to use depends on the Lumped L and C frequency of the signal:
cutoff frequency of the line !
. f_{signal }< f_{0 }=> RC line (R dominates over L) f_{signal }> f_{0 }=> LC or LRC line (L dominates over R)
Infinitesimal LRCG Wire Model
.Model an infinitesimal length of wire, dx, with the components:

– L = series inductance per unit length

– R = series resistance per unit length

– C = parallel capacitance per unit length

– G = parallel conductance per unit length between the signal and ground wires
. Theoretical model — not usable in practical simulation tasks
Lumped LRCG Model for Simulation
.Divide the transmission line into sections of the length Δx and model each section by its lumped L, R, C and G
.If Δt is the timestep used by the simulator, and t_{r }is the shortest expected rise time in the line (i.e. 1/(2t_{r }) is the highest frequency!), then, as a rule of thumb, the length Δx should be selected in such a way that
Δt <<2πΔx LC <<2
t
r
where 1/(2πΔx
LC )is the resonant frequency of a
wire section
Transmission Line Equations
∂V∂I
= RI + L

Voltage drop across R and L : _{∂}_{x }_{∂}_{t }∂I ∂V

Current into C and G :_{∂x }^{= GV + C }_{∂}_{t }
Differentiating 1 with respect to x and substituting 2 into the result gives: ∂^{2}V ∂V ∂^{2}V
=RGV +(RC +LG) +LC
∂x^{2 }∂t ∂t^{2 }
Lossless LC lines
. .

If R and G are negligible – line is lossless (no attenuation) – governed by the wave equation Waves propagate down the line in both directions without distortion

2 2 2 2 t VLC x V ∂∂=∂∂2 1 )( −=LCv

where, 1 2 2 2 t V v ∂∂=2 1 0 ⎟⎠⎞⎜⎝⎛=C LZ

.

Line is described by its impedance Z0 and velocity v



Lossless LC line
. The wave equation
∂^{2}V 1 ∂^{2}V ⎛−^{1 }⎞∂x^{2 = }v^{2 }∂t^{2 }^{⎜⎜}_{⎝ }^{v }^{=(}^{LC}^{)}^{2 }^{⎟⎟}_{⎠ }
has solutions of the form:
V_{f }(x,t) =V ⎜^{⎛}0,t −^{x }⎟^{⎞ }_{(Forward wave)
}⎝ v ⎠
_{V }_{(}_{x}_{,}_{t}_{) = }_{V }_{⎜}^{⎛ }_{x }_{,}_{t }_{− }^{x}^{max − }^{x }_{⎟}^{⎞ }(Reverse wave
)
r max
⎝ ^{v }⎠
. Waveform on the line is superposition of forward and reverse traveling waves !!
Driving a Transmission Line
.Place waves on the line by driving one end with a voltage source V(t) which has an output impedance R_{0}. Assume that the line is infinite for now.
Driving a Line —Equivalent Circuit
.Response of the line to the voltage source V(t) depends on the previous state of the line, i.e., the voltage V_{C }to which the capacitance C of the line has been previously charged
.When V_{C }= 0, the wave propagating along the line is said to be the first incident wave
Load Termination
.Suppose we drive a unit step U(t) on the line which is terminated in an impedance of Z_{T }
. What happens in the far end?
Incident wave, i.e., forward traveling wave injected into the line
Termination —Equivalent Circuit
V_{i }= amplitude of the incident wave at the end of the line ( = V_{i }(x_{max},t) )
.In the model, the voltage is 2V_{i }or twice the amplitude of the incident wave at the end of the line in order to get the voltage V_{i }on the line when Z_{T }= Z_{0 }(dividebytwo voltage divider)
Some Common Terminations
Opencircuit termination
Z_{T }− Z_{0}
k =
r
Z_{T }+ Z_{0 }
Z_{T }=∞, k_{r }= 1
Reflection doubles the voltage !
Z_{T }= Z_{0}, k_{r }= 0
No reflection !
Z_{T }=0, k_{r }=−1
Reflection cancels the voltage !
Reflections
.Incident wave determines V_{i }, I_{i }.Use the equivalent circuit to solve for V_{T }, I_{T }.Use superposition to calculate V_{r }, I_{r}
_{ }
k_{r }=
KTH/LiRong Zheng
Matched Termination
Series Source Termination
SourceTerminated Line
.Half of V_{T }is first injected into the line (dividebytwo voltage divider !). A full reflection at the receiver side doubles V_{B }to the full amplitude. V_{A }at the transmitter side follows one line delay later.
. Source termination prevents multiple reflections and absorbs noise at the source.
.Many systems provide matched terminations for both ends of the line.
Example of Reflections
_{k = }T 0
r
Z_{T }+ Z_{0 }
Example of Reflections
1000
Vline =⋅1V
max
400 +1000 = 0.714 V
Without a matched termination at least at one end of the line a significant delay or intersymbol interference is introduced !!
Tunable Segmented Matched Line Driver
Equivalent Output resistance R_{eq}= Z_{o
}
Parallel Termination─ Transistors as Resistors
^{V}dd ^{R}
^{ }
)
V
2 M_{r }1.9 NMOS only
1.8
1.7
PMOS only
Out 1.6
1.5
1.4 ^{V}dd ^{V}dd 1.3
1.2 _{M}_{r }_{1.1 }PMOS with1V bias
1
N
o
r
m
liz
d
R
s
is
t
n
c
(
V_{bb }0 0.51 1.5 2 2.5 V_{R }(Volt
)
Out Out
Output Driver with Varying Terminations
V
DD
V
in
4 V 3
2 2
1 1
0 0
1 0123456781 time (sec)
012345678
Lossy Transmission lines
Lossy Transmission Lines
.LC lines with resistance R and conductance G

– propagation governed mostly by the wave equation (LC)

– … and some by the diffusion equation (RC)
.R and G dissipation

– reduces the amplitude of the signal

– disperses the signal » fast rise to AC (wave) attenuation » slow tail to DC attenuation
. Resistance and conductance depend on frequency
– we return to this a bit later
Example: Step Response of a 1 m/0.2 mm Stripline
Wave Attenuation
.The magnitude of the traveling wave, V_{i }(x), at .Using Taylor series we get: any point x of the line is related to the initial magnitude V_{i }(0) by A ≈j
ω
LC _{⎜}⎜^{⎛}1− j ^{RC }^{+ }^{GL }_{⎟}⎟^{⎞ }
_{⎝ }2ωLC _{⎠
}V_{i }(x) =V_{i }(0)exp(−Ax) _{or }^{V}^{i }^{(}^{x}^{) }_{=exp(−}_{Ax}_{)}1
V_{i }(0)
= jω LC + ^{R }+ ^{GZ}^{0}, Z_{0 }=^{⎛}⎜ ^{L }^{⎞}⎟ ^{2}
^{ }
2Z_{0 }
2 ⎝ C ⎠
where A =[(G +jωC)(R +jωL)]^{1}2
is the propagation constant of the line^{Phase shift Amplitude loss}
^{ }
.Assuming that G and R are relatively small .Hence, the amplitude at any point x, with at high frequencies we can rewrite A as respect to the initial amplitude, can be written as
1
A ≈( jωRC +jωGL −ω^{2 }LC)^{2 }V (x) _{=exp[−(α}_{R }_{+α}_{D }_{)}_{x}
_{]}
i
^{1}V_{i }(0)⎛RC +GL ⎞^{2 }^{= jω LC}
^{ }
_{⎝}⎜^{⎜1− j }_{ω}_{LC }_{⎠}⎟^{⎟ }where the attenuation factors α_{R }and α_{D }are given by
_{α}_{R }_{= }^{R }Loss in the resistance R _{2}_{Z }per unit length
0
_{α}_{D }_{= }^{GZ}0 Dielectric loss in the conductance G 2 per unit length
DC Attenuation
. DC conductance of the dielectric (insulator) is zero in most real transmission lines. Hence, only the resistance of the conductor causes a significant DC attenuation
.Consider a line of the length d with the matched termination Z_{0}. The output voltage across Z_{0}, denoted V_{DC}(d), is related to the initial DC voltage V_{T }by
V_{DC }(d ) _{= }Z_{0 = }1
V_{T }Rd + Z_{0}2α_{R}d +1
α_{R }= ^{R }(Attenuation factor)2Z_{0 }
Attenuated Waveform
Attenuation Closes the Eye Diagram
.Critical parameter is what fraction of swing, A, is obtained in one bit time
.Eye opening is reduced to B = 2A1
.No eye opening at 50 % attenuation (A =
0.5 => B = 0)
. Significant degradation of margins at lower levels of attenuation
Skin Effect
.Current density J in a conductor drops off exponentially with depth d
.Skin depth δis the depth where the current has decreased to 1/e (37 %) of its maximum value on the conductor surface
.Skin depth δdepends on the frequency f of the traveling signal, the conductivity σ[1/resistivity (ρ)] of the wire material, and the permeability μof the surrounding medium
.Because δ~ f ^{½}, highfrequency currents flow primarily on the surface of a conductor !!
.Skin effect is modeled by assuming that all current flows in the δthick outer layer of the conductor. The crosssectional area A that is carrying current is then
_{given by: }Rectangular wire:
δ
1
A ≈2πrδ=2πr(πfμσ)^{− }^{2 }(Round wire) ^{h}
^{ }
δ
1
A ≈2wδ=2w(πfμσ)^{− }^{2 }(Rectangular wire) ^{w}
^{ }
KTH/LiRong Zheng
SkinEffect Resistance
.Effect occurs when the signal frequency exceeds the skin depth frequency f_{s }, where the skin depth is equal to the radius r of a round conductor or half of the height h of a rectangular conductor:
ρ ρ
^{f}s ^{=}_{πμ r}2 (Round wire) ^{f}s ^{=}_{πμ(}_{h }_{/2)}2 (Rectangular wire)
.Skineffect resistance R(f) per unit length, where f ≥f_{s }, is given as
_{1 }1
R( f ) =^{1 }⎜^{⎛ }^{f}^{μρ}⎟^{⎞ 2 }= ^{RDC }_{⎜}⎜^{⎛ }^{f }_{⎟}⎟^{⎞ }^{2}, R_{DC }=^{ρ }_{2 }(Round wire)
2r _{⎝}π_{⎠ }2 _{⎝ }f_{s }_{⎠ }π r
1
1^{1 }⎛ f ⎞ ^{2 }ρ
R( f ) =(πfμρ)^{2 }= R _{⎜}⎜ _{⎟}⎟, R =(Rectangular wire)2w ^{DC }_{⎝ }f_{s }_{⎠ }^{DC }wh
.Hence, above the frequency f_{s }, the resistance increases as the squareroot of frequency !!
Resistance and Attenuation of a Stripline
1
.w = 125 μm, h = 20 μm, skineffect attenuation factor: α_{S }( f ) =^{R}^{DC }^{⎛}_{⎜}⎜ ^{f }^{⎞}_{⎟}⎟ ^{2 }2Z_{0 ⎝ }f_{s }_{⎠}
_{ }
50 Ω/m R_{DC }= 7 Ω/m
A_{DC }= 0.90 m ^{1 }
0.40 m ^{1 }
1/22/2009
Dielectric Absorption
.Highfrequency signals jiggle molecules in the insulator. Hence, the insulator absorbs signal energy !
.This effect is approximately linear with the signal frequency and is modeled as a conductance G
.Dielectric loss is often specified in terms of a loss tangent, denoted tan(δ)
KTH/LiRong Zheng
1/22/2009
where
1 c
v ==
LC ε
r
v = speed of the wavec = speed of light in vacuumε_{r }= relative permittivity of
the insulator material
SkinEffect Resistance and Dielectric Absorption
. Example: 1 m/0.2 mm stripline with GETEK dielectric
Bd^{2 }Constant
.Suppose you can tolerate a certain attenuation A
– eye opening is 2A1 .At a certain bandwidth B_{1 }attenuation A is achieved with a distance of 1 m .As the bandwidth is increased to B, resistance, and hence attenuation, is increased with B ^{½ }.In order to maintain the initial attenuation level, the distance d must be decreased so that the product Bd ^{2 }equals the initial bandwidth B_{1 }.For example, if B = 4B_{1}, the distance must
be halved. Or if the distance is doubled, the bandwidth is limited to B = B_{1}/4
A(B_{1},1m) = A_{1 }
1 ⎛B ⎞^{2 }
A(B, d ) =A_{1}d_{⎜}⎜ _{⎟}⎟ ⎝ ^{B}1 ⎠requirement: A(B, d ) =A_{1 }
⇒ Bd ^{2 }= B_{1 }
MultiDrop Buses
. At any given point in time, one module is authorized to transmit data and the other modules listen
. Any module can communicate with any other module
. Bus speed is limited by geometry of the bus:
– stub length and stub spacing
Modules
^{R}_{T }^{R}_{T }
_{Z = }^{L}v =
KTH/LiRong Zheng C
^{LC
}
1/22/2009
Example Bus
. Z_{b }= Z_{s }= 50 Ω

– C = 150 pF/m, L = 375 nH/m, Z = (L/C)^{½ }. Z_{x }= 15 pF, C_{s }= 150·0.1 pF = 15 pF (transceiver & stub capacitances)

– adds 30 pF of load every 3 cm, or 1 nF/m .Hence, the busstubtransceiver combination has a capacitance of 1.15 nF/m – m/s (1/3 of the normal speed) .Highimpedance, highswing drivers need
several round trips to ring up the lowimpedance bus to a detectable voltage level
– causes a considerable delay, together with the low ^{R}^{T
}velocity

– Example : 30 cm bus, 6 ns/traversal, 5 traversals needed => 30 ns delay (33 MHz) .A sharp signal edge traveling down the bus reflects partially back from each stub

– rise/fall time of a signal, t_{r }, must be significantly longer than the roundtrip delay t_{d }of a stub. A rule of thumb: t_{r }> 5t_{d }

– Example: t_{d }= 1.4 ns => rise/fall times must be 7 ns or longer .Leaving a module “unplugged” (a free slot) causes an impedance mismatch and hence
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significant reflections (a 50 Ωsection surrounded by 18 Ωlines )
1/22/2009 40
MultiDrop Buses vs PointtoPoint Architectures
. Pointtopoint links can signal 510 times faster than buses
. Pointtopoint architectures are rapidly replacing bus architectures in highspeed systems
Bus architecture
Pointtopoint architecture
Balanced Lines, Modeling, Design, and Wire Costs
Balanced (Symmetric) Transmission Lines
.A transmission line has a signal path and a return path (“ground”)
.All real transmission lines have a nonzero inductance also in the return path, so that the total inductance per unit length L is the sum of the inductances per unit length in the signal and return paths: L = L_{s }+ L_{r }
.For coaxial cables and striplines between large return planes L_{r }is much less than L_{s }and can often be ignored
.In a balanced line, the return
0.5 V
inductance L_{r }equals the signal _{1 V}
_{ }
1 V inductance L: L= L
s sr
– voltage drops across L_{s }and L_{r }are
equal but opposite in direction
0.5 V
Pair of Coupled Transmission Lines
. Consider a pair of signal wires which are balanced or symmetric with respect to each other, so that their inductances are equal
(L)
.M (mutual inductance) and C_{d }represent coupling between the two lines
.L and C_{c }represent coupling to other conductors
For example, a pair of strip guides between ground planes
Commonand DifferentialMode Signals
A wave has two possible propagation modes: .Commonmode signal ^{V}^{1 }

– both lines are tied together and driven with the same
signal

– equal currents flow in the two lines in the same
direction _{V}_{2 }.Differentialmode signal

– the signal is applied differentially across the two lines

– equal currents flow in the two lines in opposite directions V_{1
}
.The voltages V_{1 }and V_{2 }applied to the two lines can ^{V}2 be viewed as the combination of a commonmode voltage V_{C }and a differentialmode voltage V_{D }
_{V}_{C }_{= }^{V}1 ^{+}^{V}2 _{V}_{D }_{= }^{V}1 ^{−V}2 Example: 1 V step (V_{1}=1 V, V_{2}=0): 22 V_{C }= 0.5 V, V_{D }= 0.5 V
Commonand DifferentialMode Impedance
. Common mode

– parallel currents increase the effective inductance by M

– parallel voltage transitions cancel the effect of C_{d }
1 _{Z}_{C }_{= }V_{C }_{=}⎛_{⎜⎜ }L +M ⎞_{⎟⎟ }^{2 }I_{1 ⎝ }C − C_{d }_{⎠ }
_{. Differential mode }. Commonand differentialmode signals
– opposite currents reduce the effective ^{see different impedances! }inductance by M .Increasing the coupling capacitance C_{d}, – opposite voltage transitions double the ^{for example by reducing the distance }effect of C_{d }between the two wires, gives a better 1 differential line, as Z_{D }is reduced and Z_{C }_{Z = }^{V}D _{=⎜⎜}^{⎛ }^{L − M }_{⎟⎟}^{⎞}^{2 }is increased
D
I_{1 ⎝ }C + C_{d }_{⎠ }
Example of Commonand DifferentialMode Impedances
Termination of a Balanced Line
.In a balanced termination, the commonand differentialmode impedances are matched simultaneously

– commonmode signals terminated with the impedance Z_{C }

– differentialmode signals terminated with the impedance Z_{C } R_{P }which equals Z_{D}, if
^{R}P
=
2
⎛⎜⎜⎝
^{Z}D^{Z}C
Z
⎞⎟⎟⎠
C
−
Z
D
.Unbalanced termination causes mode coupling, i.e., energy is exchanged between the commonmode wave and the differentialmode wave at each reflection
– leads to intersymbol interference
Modeling of Real Signal Paths
. Given a real system
– chips, packages, boards, connectors, backplanes, cables
.Need to develop a model of the signaling medium
– for hand calculation of key properties
– for SPICE simulations . Model must

– capture all relevant wire properties » transmission line properties » major discontinuities » terminations

– ignore properties that are not relevant » for example short discontinuities
Example Model
Deriving and Using a Model
. Create first detailed physical models of the line components (striplines, cables, connectors, packages, etc.)
– use data books provided by the component vendors
. Create an electrical model by computing the electrical parameters from the physical model
– hand calculation
– a CAD tool . Simulate the electrical model using for example SPICE . Validate the electronic model in the laboratory after the components of the
line have been fabricated
– use for example the timedomain reflectometer (TDR )
Wire Costs — Area
.Modern digital chips are often wirelimited, i.e., the area (and hence the cost) of a chip is determined by the required wiring rather than the number of transistors.
.The area of a chip is expressed as the number of wire grids
– number of grids = horizontal tracks * vertical tracks .A grid has a technologydependent cost –0.35 μm technology in 1996: unit cost = 3.1 ·10 ^{7 }$/grid, => 15*15 mm^{2 }chip with 1.6 ·10^{8 }grids: cost = $50
. Offchip wiring on a circuit board is 1001000 times more expensive per grid than the wiring on a chip
– a major reason why integration pays off !!
Wire Costs — Pins
.If a chip is pinlimited, the cost is dominated by the area required by the bonding pads. In other words, the number of I/O terminals is large compared to the size of logic and its wiring
.Selected bonding method affects the cost In 1996:
– peripheralbonded chip (pads surround the logic core): 11 cents/pin
– areabonded chip (pads utilize the entire area of the chip): 1.4 cents/pin .Selected package affects the cost

– plastic packages are inexpensive (about 1 cent/pin) but have poor electrical properties

– ceramic packages with power planes, multiple signal layers, and heat slugs can be very expensive (about 10 cents/pin)
Summary
. Transmission Line Model . Load and source termination . Lossy transmission lines . Multidrop bus . Balanced lines
Next Lecture: Noise in Digital Systems
Home reading: Ch.6
