Computer Organization and Structure hw#3 資管二 B94705007 賴威志




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Computer Organization and Structure HW#3

資管二 B94705007 賴威志

1.

Convert 4096ten, -2,047ten, and -2,000,000ten into 32-bit two’s complement binary numbers, respectively, and convert the following two’s complement binary numbers to be decimal numbers:

(1) 4096 ten = 0000 0000 0000 0000 0001 0000 0000 0000 two

One’s complement = 1111 1111 1111 1111 1110 1111 1111 1111 two

= 1111 1111 1111 1111 1111 0000 0000 0000 two

(2) 2047 ten = 0000 0000 0000 0000 0000 0111 1111 1111 two

One’s complement = 1111 1111 1111 1111 1111 1000 0000 0000 two

-2047 ten = two’s complement = 1111 1111 1111 1111 1111 1000 0000 0001 two

(3) 2000000 ten = 0000 0000 0001 1110 1000 0100 1000 0000 two

One’s complement = 1111 1111 1110 0001 0111 1011 0111 1111 two

-2000000 ten = two’s complement

= 1111 1111 1110 0001 0111 1011 1000 0000 two


(a) 1111 1111 1111 1111 1111 1111 0000 0110two

One’s complement = 0000 0000 0000 0000 0000 0000 1111 1001 two

Two’s complement = 0000 0000 0000 0000 0000 0000 1111 1010 two = 250 ten

The answer is -250 ten


(b) 1111 1111 1111 1111 1111 1111 1110 1111two

One’s complement = 0000 0000 0000 0000 0000 0000 0001 0000 two

Two’s complement = 0000 0000 0000 0000 0000 0000 0001 0001 two = 17 ten

The answer is -17 ten


(c) 0111 1111 1111 1111 1111 1111 1110 1111two = 2147483631 ten

2.

The following four instructions:

srl $s1, $s1, 1

sll $t0, $s0, 31

srl $s0, $s0, 1

or $s1, $s1, $t0

The instructions above can be considered as a shift-right-logical for two 32-bit registers instruction, or a shift-right-logical instruction for the data type “long”, consist of registers $s0 and $s1, from high digits to low digits. The srl instruction in line 1 shifts the register $s1 right by 1 digit, and the most left digit becomes 0. The instruction sll in line 2, stores the most right digit of $s0 in $t0. Line 3 shifts right the register $s0 by 1 digit. Combining the $t0 and $s1, the last line accomplishes the shift-right-logical operation for 2 registers.

3.


4.


(a-1) With guard digits

Round the sum with 3 significant digits =

(a-2) Without guard digits

The answer =


(b-1) With guard digits

Round the sum with 3 significant digits =

(b-2) Without guard digits

The sum = , off 1 in the last digit from the calculation above.


5.     

Given the bit pattern:

  1010 1101 0001 0000 0000 0000 0000 0010

 What does it represent, assuming that it is:

 (a) A two’s complement integer?

One’s complement = 0101 0010 1110 1111 1111 1111 1111 1101

Two’s complement = 0101 0010 1110 1111 1111 1111 1111 1110 = 1391460350

The Answer = -1391460350


(b) An unsigned integer?

1010 1101 0001 0000 0000 0000 0000 0010 = 2903506946


(c) A single precision floating-point number?

S

exponent

fraction

1

0101 1010

001 0000 0000 0000 0000 0010

1

90




(d) A MIPS instruction?

op

rs

rt

rd

address/shamt

funct

101011

01000

10000

0000 0000 0000 0010

43

8

16

3

opcode 43 = sw (store word)

The first register source operand 8 = $t0

The second register source operand16 = $s0



The address is 2

Therefore the instruction is: sw $s0,2($t0)


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