Cadence allegro input Processor fabmaster software f




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CADENCE ALLEGRO Input Processor

FABmaster software V8.F

December 2000


Table of Contents

This datasheet contains information specific to the FABmaster CADENCE ALLEGRO input processor. For a broader description of how to run input processors on FABmaster see the reference document "FABmaster Standard Input Documentation".



1. FABmaster CADENCE ALLEGRO Input Processor 3

1.1 Introduction 3

1.2 About the Input Processor 3

2. Before Running the Input Processor 3

2.1 Data Extraction 3

3. Running the FABmasterCADENCE ALLEGRO Input Processor 5

3.1 File Accessibility 5

3.2 FABmaster CADENCE ALLEGRO Configuration Files 5

4. Temporary Library Attribute Files 5

4.1 DEVICE.ATT & OUTLINE.ATT Files 6

5. Sample Cadence Allegro ASCII File 7

5.1 File Extracts 7



FOR YOUR INFORMATION

 The datasheet uses the input processor with classic FABmaster software application.



Symbols used throughout this document:

<> = the Enter key. All key commands are shown between angle brackets (< >)
e.g. <Tab> the Tab key, <Ins> the Insert key, <Y> the character Y, etc.

L = Left Mouse button.

R = Right Mouse button.

Running / Selecting icons, keyboard commands or dialog boxes:

To run an icon: move the cursor over the icon and key <> or double-clickL.

To run or execute a command or dialog box prompt: key <> or single-click L.

To select an icon or command for processing: key <Ins> or single-click R.



A feature in FABmaster for Windows includes the on-line Help accessed by keying <F1> or clicking on the Help button.

1.FABmaster CADENCE ALLEGRO Input Processor

1.1Introduction


This datasheet is specific to the FABmaster CADENCE ALLEGRO input processor and should be read in conjunction with the more general "FABmaster Standard Input Documentation" as it contains much more conventional information including:

  • A general procedure to follow before running the input processor (possible disk space problems, file transferal, …).

  • Managing attribute data should temporary Library Attribute (.ATT) files be generated.

  • The configuration file default names, a summary of their contents and their location.

  • Step by step instructions for running an input processor on FABmaster.

1.2About the Input Processor


CADENCE ALLEGRO (for Unix) printed circuit databases must be extracted from the ALLEGRO CAD system using the Extraction Script File software which is delivered with the input processor.

This extraction software has been tested with ALLEGRO Versions 4.0, 5.0, 6.1, 8.0, 10.0, 11.0, 11.5, 12 & 13. If the user has more than one version of the ALLEGRO CAD system, the extraction file must be run on the most recent version.

When the extraction software is run, it generates a single ASCII output file (.VAL) containing the printed circuit database. The file is then transferred from the ALLEGRO CAD system via a network or serial line to the system where FABmaster is installed and the input processor is run to convert the ASCII file into the FABmaster neutral database format.

The CADENCE input processor includes configuration files with user-programmable parameters.


2.Before Running the Input Processor

2.1Data Extraction


To convert a printed circuit board from an ALLEGRO CAD system, the database must first be extracted as an ASCII file using the Cadence Allegro Data Extract utility which is controlled by the FABmaster script file.

The FABmaster script file describes the data to be extracted from the database. The ensuing instructions are for the UNIX extraction program. Please see the documentation for the Windows extraction program (CDS2FAB) if you have a Windows-based version of CADENCE.

Before running the extraction file, ensure all the necessary UNIX Read, Write and Execute privileges are installed, if not problems may arise. This program must be run on the system where your ALLEGRO CAD system is installed.

If TEST PREP is to be used, all TEXT and LABEL generation must be f before running TEST PREP. This means TEXT NOTATION has to be f and the ISOPLOT option disabled.

The word GEOMETRY may need to be changed to FULL_GEOMETRY in the extraction file if there are problems reading the file into FABmaster.

This program must be run in a UNIX window. The ALLEGRO software must be accessible and in the user's PATH because the script needs to access the ALLEGRO Extract utility.

When the script file CDS2FAB is run (in certain ALLEGRO CAD systems, the script file CDS2FAB is called VALIDFAB - note that VALID is the ex-name of CADENCE ALLEGRO), a single ASCII output file is generated which includes all the data required for the input processor. Copy this file into the directory containing the PCB design file to be extracted, or create a new directory and copy the design file and CDS2FAB into it.

Once in a UNIX window, type:



CDS2FAB BOARD_NAME.BRD FABNAME.VAL <>

CDS2FAB

Name of the Extraction Script file.

BOARD_NAME.BRD

Name of the board to be extracted followed by the extension .BRD.

FABNAME.VAL

Output file name for FABmaster. Must be DOS-compatible.

Note 1: If the SHELL environment is /bin/csh, the user must ensure that the first line of the script file reads # If the SHELL environment is not /bin/csh, type the line csh -c filename .

Note 2: If the file will not "execute", type: chmod a+x filename.

Note 3: On certain systems, you may get a "final not found" error. As long as the program generates a normal .VAL file that loooks basically like the sample file at the end of the datasheet, this error can be ignored.

The extracted database is made up of 8 separate sections,each one consists of 3 type of lines:



Line 1, Column 1 is an A line beginning 'A!'. Followed by the name of the section and description of the field parameters.

Line 2, Column 1 is a J line beginning 'J!'. Followed by board design information.

Line 3 onwards, Column 1 is an S line, beginning 'S!'.

Example:

A!NET_NAME!REFDES!PIN_NUMBER!PIN_NAME!PIN_GROUND!PIN_POWER!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!A12VSYS!J10!1!J1!!!

We recommend the user copies the final file(s) into a sub-directory where he keeps his CAD files, for example: C:\CADFILES\CADENCE.

 It is best not to copy them into the \academi directory.

The Cadence Allegro input processor is run to convert the ASCII file into the FABmaster neutral database format.

3.Running the FABmasterCADENCE ALLEGRO Input Processor

3.1File Accessibility


Before starting, make sure that the job file is in a directory which can be accessed directly by FABmaster.

After checking that the parameters have been set up correctly in the machine configuration files the input processor can be run. Look at IPERROR.ASC to see if any errors have been reported. Correct them and re-run the output processor.



See §5 in the FABmaster Standard Input Processor reference document for a step-by-step procedure to run an input processor.

3.2FABmaster CADENCE ALLEGRO Configuration Files


Various configuration files to customise the operation of the Cadence Allegro input processor are stored in the directory ACADEMI\FAB\INPUT\CADENCE.

Configuration Files

Contents

ATTRIB.INI

Defines electrical Device and physical Outline Attributes for output to the temporary files DEVICE.ATT and OUTLINE.ATT.

These attributes can be merged into the FABmaster Job Attribute Libraries (see §4).



CONFIG.INI

Contains user-programmable parameters including:

  • Board X,Y offsets,

  • auto-centring of the board.

GEOMETRY.INI

Lists the different graphics (Circle, Octagon, Cross, Square, Rectangle, Triangle, …) and whether to ignore them or not (0 << ignore).

LAYER.INI

Defines the sense (COMMON, TOP, BOTTOM, TRANSPARENT) and layer type (ELECTRICAL, ASSEMBLY, SILKSCREEN, BOARD_CUTOUT, DOCUMENTATION, MASKING) of Cadence Allegro layers.

Specifies which Cadence Allegro layers are to be ignored.

Allows the user to rename Cadence Allegro layers and group layers with the same name for assignment to the same FABmaster layer.


SECTION.INI

Interprets Cadence Allegro internal definition keywords.

FILES.INI

Locks the CAD input filepath so preventing the user from changing directory (folder).

Lists the file extension filters. The separator "|" is user-configurable. Directs the input processor to the file source location.

The other parameters are for internal FABmaster use only.



If any of these configuration files are customised we recommend that these versions are kept with the source file(s). The input processor will then use these customised versions automatically. Read the comments carefully in each file before making any modifications.

4.Temporary Library Attribute Files

4.1DEVICE.ATT & OUTLINE.ATT Files


After the input processor has run, the files DEVICE.ASC and OUTLINE.ASC may be created. These files contain attributes derived from the incoming data or attributes extracted from the FABmaster® System Libraries. Two temporary files are created, DEVICE.ATT and OUTLINE.ATT, which contain electrical Device and physical Outline Attributes extracted from the Cadence Allegro database and specified in the ATTRIB.INI configuration file.

The attributes in .ATT files should be merged into the FABmaster Job Attribute Libraries (we recommend you do it immediately after running the input processor) using the procedure described below for the device attribute files.

The procedure is identical for the Outline Attribute files using OUTLINE.ASC and OUTLINE.ATT.


  • Update the Device Attribute Library with the data in DEVICE.ASC. Click the Edit button to display the file. Exit the editor and key <Y> when prompted Update Job Library? .

  • Delete the .ASC file. Click Delete to delete the data in DEVICE.ASC. If the TEXT icon is run immediately afterwards the DEVICE.ASC will no longer be displayed in the list.

  • Rename the DEVICE.ATT file. Run the DOS icon in the Job Screen and use the DOS command RENAME to rename the file DEVICE.ATT to DEVICE.ASC by typing:

RENAME DEVICE.ATT DEVICE.ASC

Return to FABmaster by typing the DOS command EXIT.

  • A file called DEVICE.ASC which is the renamed file DEVICE.ATT re-appears in the list box ASCII text file Selection when the TEXT icon is run in the Job Screen.

To add the attributes to the Device Attribute Library, add the line MODE=MERGE to the top of the file. If not, attributes in the Device Attribute Library will be overwritten and destroyed.

Save the file, exit the text editor and when prompted: Update Job Library? , key <Y> to return to the FABmaster Job Screen.



Refer to FABmaster Part Attribute Library Management (FABLIBRARY) documentation.

5.Sample Cadence Allegro ASCII File

5.1File Extracts


A!REFDES!COMP_CLASS!COMP_PART_NUMBER!COMP_HEIGHT!COMP_DEVICE_LABEL!COMP_INSERTION_CODE!SYM_TYPE!SYM_NAME!SYM_MIRROR!SYM_ROTATE!SYM_X!SYM_Y!COMP_VALUE!COMP_TOL!COMP_VOLTAGE!COMP_RATED_CURRENT!COMP_RATED_POWER!COMP_RATED_VOLTAGE!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!R220!DISCRETE!GRES-R39-103 4S!!!!PACKAGE!SMD1206!NO!0.000!-1925.0!-1470.0!39R!2%!!!0.125W!!

S!C408!DISCRETE!GCAP-N1.0-117 4S!!!!PACKAGE!SMD0805!NO!180.000!-3550.0!-6650.0!1.0NF!10%!CMAX!!!100V!

S!R102!DISCRETE!3CRF-00007AHT 0100!!!!PACKAGE!SMD0805!NO!270.000!-3740.0!145.0!100K!1%!!!0.063W!!

S!C116!DISCRETE!3CCC-00146AAS 0100!!!!PACKAGE!SMD1206!NO!0.000!-3900.0!-400.0!470NF!-20%/+80%!CMAX!!!50V!

......

A!NET_NAME!REFDES!PIN_NUMBER!PIN_NAME!PIN_GROUND!PIN_POWER!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!A12VSYS!J10!1!J1!!!

S!A12VSYS!J10!2!J2!!!

S!GND!J10!3!J3!!!

S!GND!J10!4!J4!!!

S!A5VCD!J10!5!J5!!!

S!VCC!J10!6!J6!!!

......

A!CLASS!SUBCLASS!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!BOARD GEOMETRY!OUTLINE! << Mandatory. Contains board contour description.

S!BOARD GEOMETRY!SILKSCREEN_TOP!

S!ETCH!BOTTOM!

S!ETCH!LAY2_SIG!

S!ETCH!LAY3_GND!

S!ETCH!LAY5_VCC!

S!ETCH!TOP!

......

A!PAD_NAME!REC_NUMBER!LAYER!FIXFLAG!VIAFLAG!PADSHAPE1!PADWIDTH!PADHGHT!PADXOFF!PADYOFF!PADFLASH!PADSHAPENAME!TRELSHAPE1!TRELWIDTH!TRELHGHT!TRELXOFF!TRELYOFF!TRELFLASH!TRELSHAPENAME!APADSHAPE1!APADWIDTH!APADHGHT!APADXOFF!APADYOFF!APADFLASH!APADSHAPENAME!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!179C158P!00001!TOP!o!!CIRCLE!179.00!179.00!0.00!0.00!!!CIRCLE!178.00!178.00!0.00!0.00!208/178/20TR!!CIRCLE!188.00!188.00!0.00!0.00!!!

......

S!179C158P!00009!~BSM!o!!CIRCLE!179.00!179.00!0.00!0.00!!!!!!!!!!!!!!!!!

S!179C158P!00010!~TPM!o!!CIRCLE!50.00!50.00!0.00!0.00!!!!!!!!!!!!!!!!!

......

A!GRAPHIC_DATA_NAME!GRAPHIC_DATA_NUMBER!RECORD_TAG!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!SUBCLASS!SYM_NAME!REFDES!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!LINE!257!3212 1!6156.72!1939.00!6131.72!1889.00!0.00!!!!!ASSEMBLY_TOP!!!

S!LINE!257!3212 2!6131.72!1889.00!6181.72!1889.00!0.00!!!!!ASSEMBLY_TOP!!!

......

A!SYM_NAME!PIN_NAME!PIN_NUMBER!PIN_X!PIN_Y!PAD_STACK_NAME!REFDES!TEST_POINT!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!W2X4BERG!J8!8!4550.00!1806.00!64C43P!J10!BOTTOM!

S!W2X4BERG!J7!7!4450.00!1806.00!64C43P!J10!BOTTOM!

S!W2X4BERG!J6!6!4550.00!1906.00!64C43P!J10!BOTTOM!

S!W2X4BERG!J5!5!4450.00!1906.00!64C43P!J10!BOTTOM!

S!W2X4BERG!J4!4!4550.00!2006.00!64C43P!J10!BOTTOM!

S!W2X4BERG!J3!3!4450.00!2006.00!64C43P!J10!BOTTOM!

S!W2X4BERG!J2!2!4550.00!2106.00!64C43P!J10!BOTTOM!

S!W2X4BERG!J1!1!4450.00!2106.00!64S43P!J10!BOTTOM!

S!DOCK-B1-OUTL!!!0.00!2251.97!50C158N!!!

......

A!VIA_X!VIA_Y!PAD_STACK_NAME!NET_NAME!TEST_POINT!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!1018.75!1456.25!VIA25C13!!!

S!1018.75!1506.25!VIA40B!!BOTTOM!

S!2025.00!1000.00!VIA25C13!!!

S!2025.00!1050.00!VIA40B!!BOTTOM!

S!-81.25!1600.00!VIA25C13!!!

......

A!CLASS!SUBCLASS!GRAPHIC_DATA_NAME!GRAPHIC_DATA_NUMBER!RECORD_TAG!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!NET_NAME!

J!/cad2/designPCB/FLX150T/SPSU/b110603.brd!Mon Mar 11 09:17:42 1996!-13287.4!-17129.9!20712.6!7870.1!0.1!mils!SPSU!186.468 mil!6!UP TO DATE!

S!ETCH!BOTTOM!LINE!257!1 1!1018.75!1456.25!1018.75!1506.25!6.00!!!!!!

S!ETCH!TOP!LINE!257!2 1!1023.33!1387.42!1023.33!1451.67!6.00!!!!!!

S!ETCH!TOP!LINE!257!2 2!1023.33!1451.67!1018.75!1456.25!6.00!!!!!!

S!ETCH!BOTTOM!LINE!257!3 1!2025.00!1000.00!2025.00!1050.00!6.00!!!!!!

......

S!BOARD GEOMETRY!OUTLINE!LINE!257!3562 1!-8169.3!-8129.9!-19.7!-8129.9!0.0!!!!!!

S!BOARD GEOMETRY!OUTLINE!LINE!257!3562 2!-19.7!-8129.9!59.1!-8051.2!0.0!!!!!!

S!BOARD GEOMETRY!OUTLINE!LINE!257!3562 3!59.1!-8051.2!59.1!255.9!0.0!!!!!!

S!BOARD GEOMETRY!OUTLINE!LINE!257!3562 4!59.1!255.9!-19.7!334.6!0.0!!!!!!

......

S!MANUFACTURING!ART-IDENT-TOP-SS!LINE!257!3217 1!-965.50!397.50!-947.00!397.50!0.00!!!!!!

S!MANUFACTURING!ART-IDENT-TOP-SS!LINE!257!3218 1!-859.00!397.50!-840.50!397.50!0.00!!!!!!

.....


December 2000 © 2000 FABMASTER S.A. All rights reserved

FABmaster® is a registered trademark of FABMASTER S.A. All other trademarks are the property of their respective owners.




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