Amd opteron X4 architecture, by Fang LI The first Opteron




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AMD Opteron X4 architecture, by Fang Li
The first Opteron was released on April 22, 2003 with K8 architecture. It is design for server and workstation, and it was the first processor to implement the AMD64 instruction set architecture (known generically as K8). Opteron is in the same segment as the Intel Xeon processor. Processors based on the AMD K10 microarchitecture (codenamed Barcelona) were announced on September 10, 2007 featuring a new quad-core configuration. AMD claimed there are seven major features introduced by K10 architecture. I will focus on two of these features [1].
Feature1. AMD Balanced Smart Cache [2]: In K8 architecture each CPU core has its own L2 memory cache. There may be a problem because on the separated cache approach at some moment one core may run out of cache while the other may have unused parts on its own L2 memory cache. When this happens, the first core must grab data from the main RAM memory, even though there was empty space on the L2 memory cache of the second core that could be used to store data and prevent the first core from accessing the main RAM memory. K10 architecture added a shared L3 memory cache to solve this problem.
Feature2. Integrated DDR2 DRAM Controller with AMD Memory Optimizer Technology [3]: CPU and chipset manufacturers came with the idea of dual-channel memory, a way to access two memory modules simultaneously, as if these two 64-bit memory modules were a single 128-bit module. This doubles the memory access transfer rate, as now instead of one 64-bit data two 64-bit data can be loaded per clock cycle. The problem with dual-channel technology is that the second 64-bit data that is loaded together with the data that was originally requested is necessarily stored on the following address. If the CPU doesn’t have a use for this data B, this second load will be completely wasted, as the memory controller cannot use this parallel loading to read a data that is stored on an address that is not the following address.

The memory controller used on K10 architecture allows the CPU to load a data stored on an address different from the next address. This independency will increase the CPU performance by not wasting memory loads. Independent memory controller divided the 128-bit memory channel into two independent 64-bit memory channels for improving memory access efficiency.

References:

[1] Quad-Core AMD Opteron™ Processor Key Features http://www.amd.com/us/products/server/processors/opteron/Pages/3rd-gen-server-features.aspx.



[2] Inside AMD64 Architecture(K8 architecture) http://www.hardwaresecrets.com/article/324/7.

[3] Inside AMD K10 Architecture http://www.hardwaresecrets.com/article/480


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